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nanoamp solutions, inc. 670 n. mccarthy blvd. suite 220, milpitas, ca 95035 ph: 408-935-7777, fax: 408-935-7770 www.nanoamp.com n64t1630c1b stock no. 23357- rev e 07/05 1 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. advance information 64mb ultra-low power asynchronous cmos psram 4m 16 bits overview the n64t1630c1b is an integrated memory device containing a 64 mbit pseudo static random access memory using a self-refresh dram array organized as 4,194,304 words by 16 bits. it is designed to be compatible in operation and interface to standard 6t srams. the device is designed for low standby and operating current and includes a power-down feature to automatically enter standby mode. the device includes a zz input for deep sleep as well as several other power saving modes: partial array self refresh mode where data is retained in a portion of the array and temperature compensated refresh. both these modes reduce standby current drain. the n64t1630c1b can be operated in a standard asynchronous mode and data can also be read in a 4-word page mode for fast access times. the die has separate power rails, vccq and vssq for the i/o to be run from a separate power supply from the device core. features ? dual voltage rails for optimum power & per- formance vcc - 2.7v - 3.3v vccq - 2.7v to 3.3v ? fast cycle times t acc < 70 ns (60ns future) t pacc < 25 ns ? very low standby current i sb < 170a ? very low operating current icc < 25ma ? pasr (partial array self refresh) ? tcr (temperature compensated refresh) ball congiguration ball description table 1: product family part number package type operating temperature power supply i/o supply speed standby current (i sb ), max n64t1630c1bz bga -25 o c to +85 o c 2.7 - 3.3v 2.7 - 3.3v 70ns 170 a 123456 a lb oe a 0 a 1 a 2 zz b i/o 8 ub a 3 a 4 ce i/o 0 c i/o 9 i/o 10 a 5 a 6 i/o 1 i/o 2 d v ssq i/o 11 a 17 a 7 i/o 3 v cc e v ccq i/o 12 a 21 a 16 i/o 4 v ss f i/o 14 i/o 13 a 14 a 15 i/o 5 i/o 6 g i/o 15 a 19 a 12 a 13 we i/o 7 h a 18 a 8 a 9 a 10 a 11 a 20 48 pin bga (top view) 6 x 8 mm pin name pin function a 0 -a 21 address inputs we write enable input ce chip enable input zz deep sleep input oe output enable input lb lower byte enable input ub upper byte enable input i/o 0 -i/o 15 data inputs/outputs v cc power v ss ground v ccq power i/o only v ssq ground i/o only
stock no. 23357- rev e 07/05 2 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information figure 1: functional block diagram table 2: functional description ce we oe ub /lb zz i/o 1 1. when ub and lb are in select mode (low), i/o 0 - i/o 15 are affected as shown. when lb only is in the select mode only i/o 0 - io 7 are affected as shown. when ub is in the select mode only i/o 8 - i/o 15 are affected as shown. mode power h x x x h high z standby 2 2. when the device is in standby mode, control inputs (we , oe ), address inputs and data input/outputs are internally iso- lated from any external influence and disabl ed from exerting any influence externally. standby ll x 3 3. when we is invoked, the oe input is internally disabled and has no effect on the circuit. l 1 hdata in write active lhl l 1 hdata out read active lhh l h high z active standby 4 l l x x l high-z set register active h x x x l high-z deep sleep deep sleep table 3: capacitance 1 1. these parameters are verified in device characterization and are not 100% tested item symbol test condition min max unit input capacitance c in v in = 0v, f = 1 mhz, t a = 25 o c 6pf i/o capacitance c i/o v in = 0v, f = 1 mhz, t a = 25 o c 6pf control logic decode logic address inputs a 4 - a 21 ce we oe input/ output mux and buffers i/o 0 - i/o 7 ub lb i/o 8 - i/o 15 address 4096k x 16 memory array zz page decode logic address word address inputs a 0 - a 3
stock no. 23357- rev e 07/05 3 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information table 4: absolute maximum ratings 1 1. stresses greater than those listed above may cause permanent dam age to the device. this is a stress rating only and functiona l operation of the device at these or any other conditions above those indicated in the operating section of this specification i s not implied. exposure to absolute maximum rating cond itions for extended periods may affect reliability. item symbol rating unit voltage on any pin relative to v ss v in,out ?0.5 to v ccq +0.3 v voltage on v cc supply relative to v ss v cc ?0.2 to 3.6 v voltage on v ccq supply relative to v ss v ccq ?0.2 to 4.0 v power dissipation p d 500 mw storage temperature t stg ?55 to 150 o c operating temperature t a -25 to +85 o c table 5: operating characteristics (over specified te mperature range) item symbol comments min. max. unit supply voltage v cc 2.7 3.3 v supply voltage for i/o v ccq vcc 3.3 v input high voltage v ih 0.8v ccq v ccq +0.2 v input low voltage v il ?0.2 0.4 v output high voltage v oh i oh = -0.2ma 0.8v ccq v output low voltage v ol i ol = 0.2ma 0.2v ccq v input leakage current i li v in = 0 to v cc 1 a output leakage current i lo oe = v ih or chip disabled 1 a read/write operating current 1 1. this parameter is specified with the outputs disabled to av oid external loading effects. the user must add current required to drive output capacitance expec ted in the actual system. i cc v in =v ccq or 0v chip enabled, i out = 0 25 ma page mode operating current i ccp v in =v ccq or 0v chip enabled, i out = 0 15 ma standby current 2 v in = v cc or 0v 2. this device assumes a standby m ode if the chip is disabled (ce high). in order to achieve low standby current all inputs must be within 0.2 volts of either vcc or vss. i sb v in = v cc or 0v chip disabled v cc = v cc max, t a = 85 o c 100 170 a
stock no. 23357- rev e 07/05 4 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information figure 2: output load circuit table 6: timing test conditions item input pulse level v ss to v ccq input rise and fall ti me (10% to 90%) 1.6ns input timing reference levels 0.5 v ccq output timing reference levels 0.5 v ccq operating temperature -25 o c to +85 o c table 7: ouput load vccq r1/r2 3.0v 4.5k ? v ccq 30 pf i/o r2 r1 output load
stock no. 23357- rev e 07/05 5 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information table 8: timings item symbol -70 unit min max read cycle read cycle time t rc 70 20k ns page mode cycle time t pc 25 ns address access time t aa 70 ns page mode access time t pa 25 ns chip enable to valid output t co 70 ns output enable to valid output t oe 20 ns byte select to valid output t bo 70 ns chip enable to low-z output t lz 10 ns output enable to low-z output t olz 5ns byte select to low-z output t blz 10 ns chip disable to high-z output t hz 08ns output disable to high-z output t ohz 08ns byte select disable to high-z output t bhz 08ns output hold from address change t oh 5ns write cycle write cycle time t wc 70 20k ns page mode max write cycle t pgmax 20k ns chip enable active time t ce 20k ns chip enable high time t ceh 5ns chip enable to end of write t cw 70 ns address valid to end of write t aw 70 ns byte select to end of write t bw 70 ns chip enable to low-z t lz 10 ns write pulse width t wp 45 ns write recovery time t wr 0ns write to high-z output t whz 08ns address setup time t as 0ns data to write time overlap t dw 25 ns data hold from write time t dh 0 ns end write to low-z output t ow 5ns we high time t weh 7.5 ns page write cycle time t pwc 25 ns page mode data to write time overlap t pdw 20 ns page mode data hold from write time t pdh 0ns
stock no. 23357- rev e 07/05 6 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information figure 3: timing of read cycle (ce = oe = v il , we = v ih ) figure 4: timing wavefo rm of read cycle (we =v ih ) address data out t rc t aa t oh data valid previous data valid address lb , ub oe data valid t rc t aa t co t hz t ohz t bhz t olz t oe t lz high-z data out t bo t blz ce
stock no. 23357- rev e 07/05 7 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information figure 5: timing waveform of page mode read cycle (we =v ih ) address lb , ub oe data valid t rc t aa t co t hz t ohz t bhz t olz t oe t lz high-z data out t bo t blz ce data valid data valid data valid t pa t pa t pa t oh t pc t pc
stock no. 23357- rev e 07/05 8 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information figure 6: timing wavefo rm of write cycle (we control) figure 7: timing wavefo rm of write cycle (ce control) address data in ce lb , ub data valid t wc t aw t cw t wr t whz t dh high-z we data out high-z t ow t as t wp t dw t bw t ce address we data valid t wc t aw t cw t wr t dh lb , ub data in high-z t as t wp t dw t bw data out t whz ce t ce t z
stock no. 23357- rev e 07/05 9 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information figure 8: timing wavefo rm of write cycle (ub , lb control) address we data valid t wc t aw t cw t wr t dh lb , ub data in high-z t as t wp t dw t bw data out t whz ce t lz
stock no. 23357- rev e 07/05 10 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information figure 9: timing waveform fo r sucessive we write cycles lb , ub we t wp t dw high-z data in ce address t wc t dh t as t wp t wr t dw t dh t wr t as t weh
stock no. 23357- rev e 07/05 11 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information figure 10: timing waveform of page mode write cycle page address (a4 - a21) lb , ub we t wp t cw t dw high-z data in t lbw, t ubw ce word address (a0 - a3) t wc t pwc t dh t pdw t pdh t ceh t pdw t pdh t as t pgmax means any page address (a4-a21) must be changed at least once in a 20us period t pgmax
stock no. 23357- rev e 07/05 12 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information power up requirements after power is applied to bring vcc and vccq up, ce should be brought high. once ce is high, a 150 s delay is required to ensure proper operation. after a 150 s delay, the device is now ready for operation or programming of the mode register.
stock no. 23357- rev e 07/05 13 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information power savings modes in the n64t1630c1b device there are several power savings modes. the three modes are: ? partial array self refresh ? temperature compensated refresh ? deep sleep mode the operation of the power saving modes is controlled by the settings of bits contained in the mode regis- ter. this definition of the mode register is shown in figure 11 and the various bits are used to enable and disable the various low power modes as well as enabling page mode operation. the mode register is set by using the timings defined in figure 12. 1) partial array self refresh (par) in this mode of operation, the internal refresh operat ion can be restricted to a 16mb, 32mb or 48mb portion of the array. the array partition to be refreshed is determined by the respective bit settings in the mode register. the register settings for the pasr operatio n are defined in table 10. in this pasr mode, when zz is active low, only the portion of the array that is set in the register is refreshed. the data in the remain- der of the array will be lost. the pasr operating mode is only available during standby time (zz low) and once zz is returned high, the device resumes full array refr esh. all future pasr cycles will use the contents of the mode register that has been previously set. to change the address space of the pasr mode, the mode register must be reset using the previously def ined procedures. for pasr to be activated, the reg- ister bit, a4 must be set to a ?1? value, ?pasr enabled?. if this is the case, pasr will be activated 10us after zz is brought low. if the a4 register bit is set equal to ?0?, pasr will not be activated. 2) temperature com pensated refresh (tcr) in this mode of operation, the in ternal refresh rate can be optimized for the operating temperature used an this can then lower standby current. the dram array in the psram must be refreshed internally on a reg- ular basis. at higher temperatures, the dram cell must be refreshed more often than at lower temper- tures. by setting the temperature of operation in the mode register, this refresh rate can be optimized to yield the lowest standby current at the given operating temperature. there are four different temperature settings that can be programmed in to the psram. these are defined in figure 11. 3) deep sleep mode in this mode of operation, the internal refresh is turn ed off and all data integrity of the array is lost. deep sleep is entered by bringing zz low with the a4 register bit set to a ?0?, ?deep sleep enabled?. if this is the case, deep sleep will be entered 10us after zz is brought low. the device will remain in this mode as long as zz remains low. if the a4 regi ster bit is set equal to ?1?, deep sleep will not be activated. other mode regi ster settings the page mode operation can also be enabled and di sabled using the mode register. register bit a7 controls the operation of page mode and setting this bit to a ?1?, enables page mode. if the register bit a7 is set to a ?0?, page mode operation is disabled.
stock no. 23357- rev e 07/05 14 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information figure 11: mode register figure 12: mode register update timings (ub , lb , oe are don?t care) deep sleep enable/disabl e 0 = deep sleep enabled 1 = pasr enabled (default) pasr section 1 1 1 = top 1/4 array 1 1 0 = top 1/2 array 1 0 1 = top 3/4 array 1 0 0 = no pasr 0 1 1 = bottom 1/4 array 0 1 0 = bottom 1/2 array 0 0 1 = bottom 3/4 array 0 0 0 = full array (default) reserved must set to all 0 a21 - a10 a7 a6 a5 a4 a3 a2 a1 a0 page mode 0 = page mode disabled (default) 1 = page mode enabled te m p compensated refresh 1 0 = 15 o c 0 1 = 45 o c 0 0 = 70 o c 1 1 = 85 o c (default) reserved must set to ?0? a9 - a8 page length 0 0 = 16 words 0 1 = 32 words 1 0 = 64 words 1 1 = 128 words address zz t wc t as ce we t zzwe t aw t wp t wr t cdzz t cw
stock no. 23357- rev e 07/05 15 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information figure 13: deep sleep mo de - entry/exit timings table 9: mode register up date and deep sleep timings item symbol min max unit note chip deselect to zz low t cdzz 5ns zz low to we low t zzwe 10 500 ns write register cycle time t wc 70/85 ns 1 chip enable to end of write t cw 70/85 ns 1 address valid to end of write t aw 70/85 ns 1 write recovery time t wr 0ns address setup time t as 0ns write pulse width t wr 40 ns deep sleep pulse width t zzmin 10 us deep sleep recovery t r 150 us 1) minimum cycle time for writing regist er is equal to speed grade of product. table 10: address patterns for pasr (a4 = 1) a2 a1 a0 active section address space size density 111top quarter of die 300 000h - 3fffffh 1mb x 16 16mb 110top half of die 200 000h - 3fffffh 2mb x 16 32mb 101top three quarter of die 100 000h - 3fffffh 3mb x 16 48mb 100no pasr none 0 0 011bottom quarter of die 000 000h - 0fffffh 1mb x 16 16mb 010bottom half of die 000 000h - 1fffffh 2mb x 16 32mb 001bottom three quarter of die000 000h - 2fffffh 3mb x 16 48mb 000full array 000 000h - 3fffffh 4mb x 16 64mb zz t zzmin t cdzz t r ce
stock no. 23357- rev e 07/05 16 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information table 11: deep icc char acteristics for n64t1630c1b item symbol test array partition typ max unit pasr mode standby current i pasr v in = v cc or 0v, chip disabled, t a = 85 o c none 70 a 1/4 array 105 1/2 array 110 3/4 array 115 full array 170 item symbol max temperature typ max unit temperature compensated refresh current i tcr 15 o c 70 a 45 o c 85 70 o c 105 85 o c 170 item symbol test typ max unit deep sleep current i zz v in = v cc or 0v, chip in zz mode, t a = 25 o c 30 a
stock no. 23357- rev e 07/05 17 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information package dimensions de e = 0.75 ball matrix type sd se j k 60.10 80.10 0.375 0.375 1.125 1.375 full side view top view bottom view e d a1 ball pad corner (3) 0.900.10 0.230.05 0.15 0.08 z z 1. 0.300.05 dia. 1. dimension is measured at the maximum solder ball diameter. parallel to primary z. 2. primary datum z and seating plane are defined by the spherical crowns of the solder balls. 3. a1 ball pad corner i.d. to be marked by ink. 2. seating plane - z sd se e k typ j typ e a1 ball pad corner
stock no. 23357- rev e 07/05 18 the specifications of this device are subject to change wit hout notice. for latest documentation see http://www.nanoamp.com. nanoamp solutions, inc. n64t1630c1b advance information figure 14: ordering information ? 2004 nanoamp solutions, inc. all rights reserved. nanoamp solutions, inc. ("nanoamp") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. nanoamp does not convey any license under its patent rights nor the rights of others. charts, drawings and schedules contained in this data sheet are provided for illustration pur- poses only and they vary depending upon specific applications. nanoamp makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does nanoamp ass ume any liability arising out of the application or use of any product or circuit described herein. nanoamp does not authorize use of its products as critical components in any application in which the failure of the nanoamp product may be expected to result in significant injury or de ath, including life support systems and critical medical instrumen t. table 12: revision history revision date change description a june 2004 original advanced datasheet b january 2005 changed maximum vcc rating c january 2005 general update d may 2005 isb change to 170ua e july 2005 changed vih to 0.8vccq n64t1630c1bz-xx i note: add -t&r following th e part number for tape and reel. orders will be considered in tray if not noted. 70 = 70ns performance

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